1. Field of the Invention
The present invention relates generally to a multiplier circuit, and a wireless communication apparatus using the same.
2. Description of the Related Art
It is often difficult to design a semiconductor integrated circuit capable of outputting high frequency carrier waves. For example, when a circuit using a millimeter wave band of 80 GHz is designed, design parameters often approach values of parasitic elements, resulting in a high difficulty level of design because the influence of the parasitic elements should be considered in the design.
For this reason, a multiplier circuit capable of outputting a multiple wave (harmonics) having a frequency that is an integer multiple of a frequency of an input signal using a nonlinear element, such as a transistor, has attracted attention. By using the multiplier circuit, it is possible to maintain a signal (i.e., an input signal) output from an oscillator at a low frequency, and also to lower a difficulty level of design for outputting high-frequency signals. For example, Japanese Laid-open Patent Application No. 2007-158803 describes an example of a frequency multiplier using a multiplier circuit.
Wireless communication apparatuses that output high-frequency signals are required to switch the output level or frequency of carrier waves according to a reception environment or applications. Therefore, in order to realize a wireless communication apparatus with a relatively low difficulty level of design, a multiplier circuit capable of adjusting the output level of a multiple wave (hereinafter, referred to as a “desired multiple wave”) multiplied by a desired multiplication number to a desired range is needed.